The present invention relates to semiconductor device fabrication and integrated circuits and, more specifically, to structures for vertical-transport field-effect transistors, as well as methods of fabricating device structures for vertical-transport field-effect transistors.
Common transistor structures include a source, a drain, a channel situated between the source and drain, and a gate electrode configured to respond to a gate voltage by selectively connecting the source and drain to each another through the channel. Transistor structures are formed on a surface of a semiconductor substrate, which surface may be considered to be contained in a horizontal plane. Transistor structures can be broadly categorized based upon the orientation of the channel relative to the surface of the semiconductor substrate.
Planar transistors constitute a category of transistor structures in which the channels are oriented parallel to the substrate surface. Vertical transistors represent a different category of transistor structures in which the channels are aligned vertical to the substrate surface. Because the gated current between the source and drain is directed through the channel, different types of vertical transistors, namely FinFETs, and vertical-transport field-effect transistors, can also be distinguished from each another based upon the direction of current flow. The gated current in the channel between the source and drain of a FinFET-type vertical transistor is generally parallel to the substrate surface. In contrast, the gated current in the channel between the source and drain in a vertical-transport field-effect transistor is generally perpendicular to the substrate surface.
Improved structures and fabrication methods are needed for vertical-transport field-effect transistors.